// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX :  
// IP Name      :      
// File name    : crossbar_ctl_top.v
// Module name  : crossbar_ctl_top
// Full name    :  
//
// Author       : lhb
// Email        : 2296971136@qq.com
// Data         : 2021/4/27
// Version      : V 1.0 
// 
// Abstract     : 
// Called by    :  
// 
// Modification history
// -----------------------------------------------------------------
// 
// 
// 
// *****************************************************************
module crossbar_4x4_top(
    input               clk,
    input               rst_n,
    input wire   [9:0]  ram_2p_cfg_register,
    //fp_and_sch_top_0--crossbar_ctl_top_0
    output              uni_tx_rdy00     ,
    output              uni_tx_rdy01     ,
    output              uni_tx_rdy02     ,
    output              uni_tx_rdy03     ,
    output              mul_tx_rdy00     ,
    output              mul_tx_rdy01     ,
    output              mul_tx_rdy02     ,
    output              mul_tx_rdy03     ,
    input [255:0]       emac_data_in0     ,
    input               emac_data_wren0  ,
    input [  5:0]       rx_address_dpram0,
    input [  3:0]       mac_dest_port_in0,
    input               mul_indicate0    ,
    //fp_and_sch_top_1--crossbar_ctl_top_1
    output              uni_tx_rdy10     ,
    output              uni_tx_rdy11     ,
    output              uni_tx_rdy12     ,
    output              uni_tx_rdy13     ,
    output              mul_tx_rdy10     ,
    output              mul_tx_rdy11     ,
    output              mul_tx_rdy12     ,
    output              mul_tx_rdy13     ,
    input [255:0]       emac_data_in1    ,
    input               emac_data_wren1  ,
    input [  5:0]       rx_address_dpram1,
    input [  3:0]       mac_dest_port_in1,
    input               mul_indicate1    ,
    //fp_and_sch_top_2--crossbar_ctl_top_2
    output              uni_tx_rdy20     ,
    output              uni_tx_rdy21     ,
    output              uni_tx_rdy22     ,
    output              uni_tx_rdy23     ,
    output              mul_tx_rdy20     ,
    output              mul_tx_rdy21     ,
    output              mul_tx_rdy22     ,
    output              mul_tx_rdy23     ,
    input [255:0]       emac_data_in2    ,
    input               emac_data_wren2  ,
    input [  5:0]       rx_address_dpram2,
    input [  3:0]       mac_dest_port_in2,
    input               mul_indicate2    ,
    //fp_and_sch_top_2--crossbar_ctl_top_3
    output              uni_tx_rdy30     ,
    output              uni_tx_rdy31     ,
    output              uni_tx_rdy32     ,
    output              uni_tx_rdy33     ,
    output              mul_tx_rdy30     ,
    output              mul_tx_rdy31     ,
    output              mul_tx_rdy32     ,
    output              mul_tx_rdy33     ,
    input [255:0]       emac_data_in3    ,
    input               emac_data_wren3  ,
    input [  5:0]       rx_address_dpram3,
    input [  3:0]       mac_dest_port_in3,
    input               mul_indicate3    ,
    //with MAC_0
    input               emac_rx_ready0   ,
    output [255:0]      pkt_data_o_0     ,
    output              pkt_dval_o_0     ,
    output              pkt_dsav_o_0     ,
    output              pkt_sop_o_0      ,
    output              pkt_eop_o_0      ,
    output [  4:0]      pkt_mod_o_0      ,
    //with MAC_1
    input               emac_rx_ready1   ,
    output [255:0]      pkt_data_o_1     ,
    output              pkt_dval_o_1     ,
    output              pkt_dsav_o_1     ,
    output              pkt_sop_o_1      ,
    output              pkt_eop_o_1      ,
    output [  4:0]      pkt_mod_o_1      ,
    //with MAC_2
    input               emac_rx_ready2   ,
    output [255:0]      pkt_data_o_2     ,
    output              pkt_dval_o_2     ,
    output              pkt_dsav_o_2     ,
    output              pkt_sop_o_2      ,
    output              pkt_eop_o_2      ,
    output [  4:0]      pkt_mod_o_2      ,
    //with MAC_3
    input               emac_rx_ready3   ,
    output [255:0]      pkt_data_o_3     ,
    output              pkt_dval_o_3     ,
    output              pkt_dsav_o_3     ,
    output              pkt_sop_o_3      ,
    output              pkt_eop_o_3      ,
    output [  4:0]      pkt_mod_o_3

);
//crossbar_ctl_top_0/crossbar_ctl_top_1/crossbar_ctl_top_2--cross_clumn_select_0
wire [255:0] emac_data_final00   ;
wire         emac_dval_final00   ;
wire         emac_dsav_final00   ;
wire         emac_sop_final00    ;
wire         emac_eop_final00    ;
wire [  4:0] emac_mod_final00    ;
wire [  3:0] mac_dest_port_out00 ;
wire         uni_cross_busy00    ;
wire         mul_cross_busy00    ;
wire         out_enable00        ;
wire [ 10:0] emac_len_final00    ;
//wire [  2:0] emac_pri_final00    ;
wire         read_finish00       ;

wire [255:0] emac_data_final10   ;
wire         emac_dval_final10   ;
wire         emac_dsav_final10   ;
wire         emac_sop_final10    ;
wire         emac_eop_final10    ;
wire [  4:0] emac_mod_final10    ;
wire [  3:0] mac_dest_port_out10 ;
wire         uni_cross_busy10    ;
wire         mul_cross_busy10    ;
wire         out_enable10        ;
wire [ 10:0] emac_len_final10    ;
//wire [  2:0] emac_pri_final10    ;
wire         read_finish10       ;

wire [255:0] emac_data_final20   ;
wire         emac_dval_final20   ;
wire         emac_dsav_final20   ;
wire         emac_sop_final20    ;
wire         emac_eop_final20    ;
wire [  4:0] emac_mod_final20    ;
wire [  3:0] mac_dest_port_out20 ;
wire         uni_cross_busy20    ;
wire         mul_cross_busy20    ;
wire         out_enable20        ;
wire [ 10:0] emac_len_final20    ;
//wire [  2:0] emac_pri_final20    ;
wire         read_finish20       ;

wire [255:0] emac_data_final30   ;
wire         emac_dval_final30   ;
wire         emac_dsav_final30   ;
wire         emac_sop_final30    ;
wire         emac_eop_final30    ;
wire [  4:0] emac_mod_final30    ;
wire [  3:0] mac_dest_port_out30 ;
wire         uni_cross_busy30    ;
wire         mul_cross_busy30    ;
wire         out_enable30        ;
wire [ 10:0] emac_len_final30    ;
//wire [  2:0] emac_pri_final30    ;
wire         read_finish30       ;
//crossbar_ctl_top_0/crossbar_ctl_top_1/crossbar_ctl_top_2--cross_clumn_select_1
wire [255:0] emac_data_final01   ;
wire         emac_dval_final01   ;
wire         emac_dsav_final01   ;
wire         emac_sop_final01    ;
wire         emac_eop_final01    ;
wire [  4:0] emac_mod_final01    ;
wire [  3:0] mac_dest_port_out01 ;
wire         uni_cross_busy01    ;
wire         mul_cross_busy01    ;
wire         out_enable01        ;
wire [ 10:0] emac_len_final01    ;
//wire [  2:0] emac_pri_final01    ;
wire         read_finish01       ;

wire [255:0] emac_data_final11   ;
wire         emac_dval_final11   ;
wire         emac_dsav_final11   ;
wire         emac_sop_final11    ;
wire         emac_eop_final11    ;
wire [  4:0] emac_mod_final11    ;
wire [  3:0] mac_dest_port_out11 ;
wire         uni_cross_busy11    ;
wire         mul_cross_busy11    ;
wire         out_enable11        ;
wire [ 10:0] emac_len_final11    ;
//wire [  2:0] emac_pri_final11    ;
wire         read_finish11       ;

wire [255:0] emac_data_final21   ;
wire         emac_dval_final21   ;
wire         emac_dsav_final21   ;
wire         emac_sop_final21    ;
wire         emac_eop_final21    ;
wire [  4:0] emac_mod_final21    ;
wire [  3:0] mac_dest_port_out21 ;
wire         uni_cross_busy21    ;
wire         mul_cross_busy21    ;
wire         out_enable21        ;
wire [ 10:0] emac_len_final21    ;
//wire [  2:0] emac_pri_final21    ;
wire         read_finish21       ;

wire [255:0] emac_data_final31   ;
wire         emac_dval_final31   ;
wire         emac_dsav_final31   ;
wire         emac_sop_final31    ;
wire         emac_eop_final31    ;
wire [  4:0] emac_mod_final31    ;
wire [  3:0] mac_dest_port_out31 ;
wire         uni_cross_busy31    ;
wire         mul_cross_busy31    ;
wire         out_enable31        ;
wire [ 10:0] emac_len_final31    ;
//wire [  2:0] emac_pri_final31    ;
wire         read_finish31       ;
//crossbar_ctl_top_0/crossbar_ctl_top_1/crossbar_ctl_top_2--cross_clumn_select_2
wire [255:0] emac_data_final02   ;
wire         emac_dval_final02   ;
wire         emac_dsav_final02   ;
wire         emac_sop_final02    ;
wire         emac_eop_final02    ;
wire [  4:0] emac_mod_final02    ;
wire [  3:0] mac_dest_port_out02 ;
wire         uni_cross_busy02    ;
wire         mul_cross_busy02    ;
wire         out_enable02        ;
wire [ 10:0] emac_len_final02    ;
//wire [  2:0] emac_pri_final02    ;
wire         read_finish02       ;

wire [255:0] emac_data_final12   ;
wire         emac_dval_final12   ;
wire         emac_dsav_final12   ;
wire         emac_sop_final12    ;
wire         emac_eop_final12    ;
wire [  4:0] emac_mod_final12    ;
wire [  3:0] mac_dest_port_out12 ;
wire         uni_cross_busy12    ;
wire         mul_cross_busy12    ;
wire         out_enable12        ;
wire [ 10:0] emac_len_final12    ;
//wire [  2:0] emac_pri_final12    ;
wire         read_finish12       ;

wire [255:0] emac_data_final22   ;
wire         emac_dval_final22   ;
wire         emac_dsav_final22   ;
wire         emac_sop_final22    ;
wire         emac_eop_final22    ;
wire [  4:0] emac_mod_final22    ;
wire [  3:0] mac_dest_port_out22 ;
wire         uni_cross_busy22    ;
wire         mul_cross_busy22    ;
wire         out_enable22        ;
wire [ 10:0] emac_len_final22    ;
//wire [  2:0] emac_pri_final22    ;
wire         read_finish22       ;

wire [255:0] emac_data_final32   ;
wire         emac_dval_final32   ;
wire         emac_dsav_final32   ;
wire         emac_sop_final32    ;
wire         emac_eop_final32    ;
wire [  4:0] emac_mod_final32    ;
wire [  3:0] mac_dest_port_out32 ;
wire         uni_cross_busy32    ;
wire         mul_cross_busy32    ;
wire         out_enable32        ;
wire [ 10:0] emac_len_final32    ;
//wire [  2:0] emac_pri_final32    ;
wire         read_finish32       ;
//crossbar_ctl_top_0/crossbar_ctl_top_1/crossbar_ctl_top_2--cross_clumn_select_3
wire [255:0] emac_data_final03   ;
wire         emac_dval_final03   ;
wire         emac_dsav_final03   ;
wire         emac_sop_final03    ;
wire         emac_eop_final03    ;
wire [  4:0] emac_mod_final03    ;
wire [  3:0] mac_dest_port_out03 ;
wire         uni_cross_busy03    ;
wire         mul_cross_busy03    ;
wire         out_enable03        ;
wire [ 10:0] emac_len_final03    ;
//wire [  2:0] emac_pri_final03    ;
wire         read_finish03       ;

wire [255:0] emac_data_final13   ;
wire         emac_dval_final13   ;
wire         emac_dsav_final13   ;
wire         emac_sop_final13    ;
wire         emac_eop_final13    ;
wire [  4:0] emac_mod_final13    ;
wire [  3:0] mac_dest_port_out13 ;
wire         uni_cross_busy13    ;
wire         mul_cross_busy13    ;
wire         out_enable13        ;
wire [ 10:0] emac_len_final13    ;
//wire [  2:0] emac_pri_final13    ;
wire         read_finish13       ;

wire [255:0] emac_data_final23   ;
wire         emac_dval_final23   ;
wire         emac_dsav_final23   ;
wire         emac_sop_final23    ;
wire         emac_eop_final23    ;
wire [  4:0] emac_mod_final23    ;
wire [  3:0] mac_dest_port_out23 ;
wire         uni_cross_busy23    ;
wire         mul_cross_busy23    ;
wire         out_enable23        ;
wire [ 10:0] emac_len_final23    ;
//wire [  2:0] emac_pri_final23    ;
wire         read_finish23       ;

wire [255:0] emac_data_final33   ;
wire         emac_dval_final33   ;
wire         emac_dsav_final33   ;
wire         emac_sop_final33    ;
wire         emac_eop_final33    ;
wire [  4:0] emac_mod_final33    ;
wire [  3:0] mac_dest_port_out33 ;
wire         uni_cross_busy33    ;
wire         mul_cross_busy33    ;
wire         out_enable33        ;
wire [ 10:0] emac_len_final33    ;
//wire [  2:0] emac_pri_final33    ;
wire         read_finish33       ;
//crossbar_ctrl_0
    crossbar_ctl_top crossbar_ctl_top_0(
            //system in/out
            .clk                (clk),
            .rst_n              (rst_n),
            .ram_2p_cfg_register(ram_2p_cfg_register),
            //with fp_and_sch_top_0
            .emac_data_in       (emac_data_in0),
            .emac_data_wren     (emac_data_wren0),
            .rx_address_dpram   (rx_address_dpram0),
            .mac_dest_port_in   (mac_dest_port_in0),
            .mul_indicate       (mul_indicate0),
            .uni_tx_rdy0        (uni_tx_rdy00),
            .uni_tx_rdy1        (uni_tx_rdy01),
            .uni_tx_rdy2        (uni_tx_rdy02),
            .uni_tx_rdy3        (uni_tx_rdy03),
            .mul_tx_rdy0        (mul_tx_rdy00),
            .mul_tx_rdy1        (mul_tx_rdy01),
            .mul_tx_rdy2        (mul_tx_rdy02),
            .mul_tx_rdy3        (mul_tx_rdy03),
            //with MAC_0
            .emac_rx_ready0     (emac_rx_ready0),  //IN 
            //with cross_clumn_select_0
            .emac_data_final0   (emac_data_final00),
            .emac_dval_final0   (emac_dval_final00),
            .emac_dsav_final0   (emac_dsav_final00),
            .emac_sop_final0    (emac_sop_final00),
            .emac_eop_final0    (emac_eop_final00),
            .emac_mod_final0    (emac_mod_final00),
            .mac_dest_port_out0 (mac_dest_port_out00),
            .uni_out_busy0      (uni_cross_busy00),
            .mul_out_busy0      (mul_cross_busy00),
            .out_enable0        (out_enable00),
            .emac_len_final0    (emac_len_final00),
            //.emac_pri_final0    (emac_pri_final00),
            .read_finish0       (read_finish00),
            //with MAC_1
            .emac_rx_ready1     (emac_rx_ready1),  //IN 
            //with cross_clumn_select_1
            .emac_data_final1   (emac_data_final01),
            .emac_dval_final1   (emac_dval_final01),
            .emac_dsav_final1   (emac_dsav_final01),
            .emac_sop_final1    (emac_sop_final01),
            .emac_eop_final1    (emac_eop_final01),
            .emac_mod_final1    (emac_mod_final01),
            .mac_dest_port_out1 (mac_dest_port_out01),
            .uni_out_busy1      (uni_cross_busy01),
            .mul_out_busy1      (mul_cross_busy01),
            .out_enable1        (out_enable01),
            .emac_len_final1    (emac_len_final01),
            //.emac_pri_final1    (emac_pri_final01),
            .read_finish1       (read_finish01),
            //with MAC_2
            .emac_rx_ready2     (emac_rx_ready2),  //IN
            //with cross_clumn_select_2
            .emac_data_final2   (emac_data_final02),
            .emac_dval_final2   (emac_dval_final02),
            .emac_dsav_final2   (emac_dsav_final02),
            .emac_sop_final2    (emac_sop_final02),
            .emac_eop_final2    (emac_eop_final02),
            .emac_mod_final2    (emac_mod_final02),
            .mac_dest_port_out2 (mac_dest_port_out02),
            .uni_out_busy2      (uni_cross_busy02),
            .mul_out_busy2      (mul_cross_busy02),
            .out_enable2        (out_enable02),
            .emac_len_final2    (emac_len_final02),
            //.emac_pri_final2    (emac_pri_final02),
            .read_finish2       (read_finish02),
            //with MAC_3
            .emac_rx_ready3     (emac_rx_ready3),  //IN
            //with cross_clumn_select_3
            .emac_data_final3   (emac_data_final03),
            .emac_dval_final3   (emac_dval_final03),
            .emac_dsav_final3   (emac_dsav_final03),
            .emac_sop_final3    (emac_sop_final03),
            .emac_eop_final3    (emac_eop_final03),
            .emac_mod_final3    (emac_mod_final03),
            .mac_dest_port_out3 (mac_dest_port_out03),
            .uni_out_busy3      (uni_cross_busy03),
            .mul_out_busy3      (mul_cross_busy03),
            .out_enable3        (out_enable03),
            .emac_len_final3    (emac_len_final03),
            //.emac_pri_final3    (emac_pri_final03),
            .read_finish3       (read_finish03)
        );

//crossbar_ctrl_1
    crossbar_ctl_top crossbar_ctl_top_1(
            //system in/out
            .clk                (clk),
            .rst_n              (rst_n),
            .ram_2p_cfg_register(ram_2p_cfg_register),
            //with fp_and_sch_top_0
            .emac_data_in       (emac_data_in1),
            .emac_data_wren     (emac_data_wren1),
            .rx_address_dpram   (rx_address_dpram1),
            .mac_dest_port_in   (mac_dest_port_in1),
            .mul_indicate       (mul_indicate1),
            .uni_tx_rdy0        (uni_tx_rdy10),
            .uni_tx_rdy1        (uni_tx_rdy11),
            .uni_tx_rdy2        (uni_tx_rdy12),
            .uni_tx_rdy3        (uni_tx_rdy13),
            .mul_tx_rdy0        (mul_tx_rdy10),
            .mul_tx_rdy1        (mul_tx_rdy11),
            .mul_tx_rdy2        (mul_tx_rdy12),
            .mul_tx_rdy3        (mul_tx_rdy13),
            //with MAC_0
            .emac_rx_ready0     (emac_rx_ready0),  //IN 
            //with cross_clumn_select_0
            .emac_data_final0   (emac_data_final10),
            .emac_dval_final0   (emac_dval_final10),
            .emac_dsav_final0   (emac_dsav_final10),
            .emac_sop_final0    (emac_sop_final10),
            .emac_eop_final0    (emac_eop_final10),
            .emac_mod_final0    (emac_mod_final10),
            .mac_dest_port_out0 (mac_dest_port_out10),
            .uni_out_busy0      (uni_cross_busy10),
            .mul_out_busy0      (mul_cross_busy10),
            .out_enable0        (out_enable10),
            .emac_len_final0    (emac_len_final10),
            //.emac_pri_final0    (emac_pri_final10),
            .read_finish0       (read_finish10),
            //with MAC_1
            .emac_rx_ready1     (emac_rx_ready1),  //IN 
            //with cross_clumn_select_1
            .emac_data_final1   (emac_data_final11),
            .emac_dval_final1   (emac_dval_final11),
            .emac_dsav_final1   (emac_dsav_final11),
            .emac_sop_final1    (emac_sop_final11),
            .emac_eop_final1    (emac_eop_final11),
            .emac_mod_final1    (emac_mod_final11),
            .mac_dest_port_out1 (mac_dest_port_out11),
            .uni_out_busy1      (uni_cross_busy11),
            .mul_out_busy1      (mul_cross_busy11),
            .out_enable1        (out_enable11),
            .emac_len_final1    (emac_len_final11),
            //.emac_pri_final1    (emac_pri_final11),
            .read_finish1       (read_finish11),
            //with MAC_2
            .emac_rx_ready2     (emac_rx_ready2),  //IN
            //with cross_clumn_select_2
            .emac_data_final2   (emac_data_final12),
            .emac_dval_final2   (emac_dval_final12),
            .emac_dsav_final2   (emac_dsav_final12),
            .emac_sop_final2    (emac_sop_final12),
            .emac_eop_final2    (emac_eop_final12),
            .emac_mod_final2    (emac_mod_final12),
            .mac_dest_port_out2 (mac_dest_port_out12),
            .uni_out_busy2      (uni_cross_busy12),
            .mul_out_busy2      (mul_cross_busy12),
            .out_enable2        (out_enable12),
            .emac_len_final2    (emac_len_final12),
            //.emac_pri_final2    (emac_pri_final12),
            .read_finish2       (read_finish12),
            //with MAC_3
            .emac_rx_ready3     (emac_rx_ready3),  //IN
            //with cross_clumn_select_3
            .emac_data_final3   (emac_data_final13),
            .emac_dval_final3   (emac_dval_final13),
            .emac_dsav_final3   (emac_dsav_final13),
            .emac_sop_final3    (emac_sop_final13),
            .emac_eop_final3    (emac_eop_final13),
            .emac_mod_final3    (emac_mod_final13),
            .mac_dest_port_out3 (mac_dest_port_out13),
            .uni_out_busy3      (uni_cross_busy13),
            .mul_out_busy3      (mul_cross_busy13),
            .out_enable3        (out_enable13),
            .emac_len_final3    (emac_len_final13),
            //.emac_pri_final3    (emac_pri_final13),
            .read_finish3       (read_finish13)
        );

//crossbar_ctrl_2
    crossbar_ctl_top crossbar_ctl_top_2(
            //system in/out
            .clk                (clk),
            .rst_n              (rst_n),
            .ram_2p_cfg_register(ram_2p_cfg_register),
            //with fp_and_sch_top_0
            .emac_data_in       (emac_data_in2),
            .emac_data_wren     (emac_data_wren2),
            .rx_address_dpram   (rx_address_dpram2),
            .mac_dest_port_in   (mac_dest_port_in2),
            .mul_indicate       (mul_indicate2),
            .uni_tx_rdy0        (uni_tx_rdy20),
            .uni_tx_rdy1        (uni_tx_rdy21),
            .uni_tx_rdy2        (uni_tx_rdy22),
            .uni_tx_rdy3        (uni_tx_rdy23),
            .mul_tx_rdy0        (mul_tx_rdy20),
            .mul_tx_rdy1        (mul_tx_rdy21),
            .mul_tx_rdy2        (mul_tx_rdy22),
            .mul_tx_rdy3        (mul_tx_rdy23),
            //with MAC_0
            .emac_rx_ready0     (emac_rx_ready0),  //IN 
            //with cross_clumn_select_0
            .emac_data_final0   (emac_data_final20),
            .emac_dval_final0   (emac_dval_final20),
            .emac_dsav_final0   (emac_dsav_final20),
            .emac_sop_final0    (emac_sop_final20),
            .emac_eop_final0    (emac_eop_final20),
            .emac_mod_final0    (emac_mod_final20),
            .mac_dest_port_out0 (mac_dest_port_out20),
            .uni_out_busy0      (uni_cross_busy20),
            .mul_out_busy0      (mul_cross_busy20),
            .out_enable0        (out_enable20),
            .emac_len_final0    (emac_len_final20),
            //.emac_pri_final0    (emac_pri_final20),
            .read_finish0       (read_finish20),
            //with MAC_1
            .emac_rx_ready1     (emac_rx_ready1),  //IN 
            //with cross_clumn_select_1
            .emac_data_final1   (emac_data_final21),
            .emac_dval_final1   (emac_dval_final21),
            .emac_dsav_final1   (emac_dsav_final21),
            .emac_sop_final1    (emac_sop_final21),
            .emac_eop_final1    (emac_eop_final21),
            .emac_mod_final1    (emac_mod_final21),
            .mac_dest_port_out1 (mac_dest_port_out21),
            .uni_out_busy1      (uni_cross_busy21),
            .mul_out_busy1      (mul_cross_busy21),
            .out_enable1        (out_enable21),
            .emac_len_final1    (emac_len_final21),
            //.emac_pri_final1    (emac_pri_final21),
            .read_finish1       (read_finish21),
            //with MAC_2
            .emac_rx_ready2     (emac_rx_ready2),  //IN
            //with cross_clumn_select_2
            .emac_data_final2   (emac_data_final22),
            .emac_dval_final2   (emac_dval_final22),
            .emac_dsav_final2   (emac_dsav_final22),
            .emac_sop_final2    (emac_sop_final22),
            .emac_eop_final2    (emac_eop_final22),
            .emac_mod_final2    (emac_mod_final22),
            .mac_dest_port_out2 (mac_dest_port_out22),
            .uni_out_busy2      (uni_cross_busy22),
            .mul_out_busy2      (mul_cross_busy22),
            .out_enable2        (out_enable22),
            .emac_len_final2    (emac_len_final22),
            //.emac_pri_final2    (emac_pri_final22),
            .read_finish2       (read_finish22),
            //with MAC_3
            .emac_rx_ready3     (emac_rx_ready3),  //IN
            //with cross_clumn_select_3
            .emac_data_final3   (emac_data_final23),
            .emac_dval_final3   (emac_dval_final23),
            .emac_dsav_final3   (emac_dsav_final23),
            .emac_sop_final3    (emac_sop_final23),
            .emac_eop_final3    (emac_eop_final23),
            .emac_mod_final3    (emac_mod_final23),
            .mac_dest_port_out3 (mac_dest_port_out23),
            .uni_out_busy3      (uni_cross_busy23),
            .mul_out_busy3      (mul_cross_busy23),
            .out_enable3        (out_enable23),
            .emac_len_final3    (emac_len_final23),
            //.emac_pri_final3    (emac_pri_final23),
            .read_finish3       (read_finish23)
        );

//crossbar_ctrl_3
    crossbar_ctl_top crossbar_ctl_top_3(
            //system in/out
            .clk                (clk),
            .rst_n              (rst_n),
            .ram_2p_cfg_register(ram_2p_cfg_register),
            //with fp_and_sch_top_0
            .emac_data_in       (emac_data_in3),
            .emac_data_wren     (emac_data_wren3),
            .rx_address_dpram   (rx_address_dpram3),
            .mac_dest_port_in   (mac_dest_port_in3),
            .mul_indicate       (mul_indicate3),
            .uni_tx_rdy0        (uni_tx_rdy30),
            .uni_tx_rdy1        (uni_tx_rdy31),
            .uni_tx_rdy2        (uni_tx_rdy32),
            .uni_tx_rdy3        (uni_tx_rdy33),
            .mul_tx_rdy0        (mul_tx_rdy30),
            .mul_tx_rdy1        (mul_tx_rdy31),
            .mul_tx_rdy2        (mul_tx_rdy32),
            .mul_tx_rdy3        (mul_tx_rdy33),
            //with MAC_0
            .emac_rx_ready0     (emac_rx_ready0),  //IN
            //with cross_clumn_select_0
            .emac_data_final0   (emac_data_final30),
            .emac_dval_final0   (emac_dval_final30),
            .emac_dsav_final0   (emac_dsav_final30),
            .emac_sop_final0    (emac_sop_final30),
            .emac_eop_final0    (emac_eop_final30),
            .emac_mod_final0    (emac_mod_final30),
            .mac_dest_port_out0 (mac_dest_port_out30),
            .uni_out_busy0      (uni_cross_busy30),
            .mul_out_busy0      (mul_cross_busy30),
            .out_enable0        (out_enable30),
            .emac_len_final0    (emac_len_final30),
            //.emac_pri_final0    (emac_pri_final30),
            .read_finish0       (read_finish30),
            //with MAC_1
            .emac_rx_ready1     (emac_rx_ready1),  //IN
            //with cross_clumn_select_1
            .emac_data_final1   (emac_data_final31),
            .emac_dval_final1   (emac_dval_final31),
            .emac_dsav_final1   (emac_dsav_final31),
            .emac_sop_final1    (emac_sop_final31),
            .emac_eop_final1    (emac_eop_final31),
            .emac_mod_final1    (emac_mod_final31),
            .mac_dest_port_out1 (mac_dest_port_out31),
            .uni_out_busy1      (uni_cross_busy31),
            .mul_out_busy1      (mul_cross_busy31),
            .out_enable1        (out_enable31),
            .emac_len_final1    (emac_len_final31),
            //.emac_pri_final1    (emac_pri_final31),
            .read_finish1       (read_finish31),
            //with MAC_2
            .emac_rx_ready2     (emac_rx_ready2),  //IN
            //with cross_clumn_select_2
            .emac_data_final2   (emac_data_final32),
            .emac_dval_final2   (emac_dval_final32),
            .emac_dsav_final2   (emac_dsav_final32),
            .emac_sop_final2    (emac_sop_final32),
            .emac_eop_final2    (emac_eop_final32),
            .emac_mod_final2    (emac_mod_final32),
            .mac_dest_port_out2 (mac_dest_port_out32),
            .uni_out_busy2      (uni_cross_busy32),
            .mul_out_busy2      (mul_cross_busy32),
            .out_enable2        (out_enable32),
            .emac_len_final2    (emac_len_final32),
            //.emac_pri_final2    (emac_pri_final32),
            .read_finish2       (read_finish32),
            //with MAC_3
            .emac_rx_ready3     (emac_rx_ready3),  //IN
            //with cross_clumn_select_3
            .emac_data_final3   (emac_data_final33),
            .emac_dval_final3   (emac_dval_final33),
            .emac_dsav_final3   (emac_dsav_final33),
            .emac_sop_final3    (emac_sop_final33),
            .emac_eop_final3    (emac_eop_final33),
            .emac_mod_final3    (emac_mod_final33),
            .mac_dest_port_out3 (mac_dest_port_out33),
            .uni_out_busy3      (uni_cross_busy33),
            .mul_out_busy3      (mul_cross_busy33),
            .out_enable3        (out_enable33),
            .emac_len_final3    (emac_len_final33),
            //.emac_pri_final3    (emac_pri_final33),
            .read_finish3       (read_finish33)
        );

//cross_bar列选择
//第一列选择
    cross_clumn_select cross_clumn_select_0(
            //system in/out
            .clk               (clk),
            .rst_n             (rst_n),
            //with crossbar_ctl_top_0
            .emac_data_final0  (emac_data_final00),
            .emac_dval_final0  (emac_dval_final00),
            .emac_dsav_final0  (emac_dsav_final00),
            .emac_sop_final0   (emac_sop_final00),
            .emac_eop_final0   (emac_eop_final00),
            .emac_mod_final0   (emac_mod_final00),
            .mac_dest_port_en0 (mac_dest_port_out00[0]),
            .uni_in_busy0      (uni_cross_busy00),
            .mul_in_busy0      (mul_cross_busy00),
            .out_enable0       (out_enable00),
            .emac_len_final0   (emac_len_final00),
            //.emac_pri_final0   (emac_pri_final00),
            .read_finish0      (read_finish00),
            //with crossbar_ctl_top_1
            .emac_data_final1  (emac_data_final10),
            .emac_dval_final1  (emac_dval_final10),
            .emac_dsav_final1  (emac_dsav_final10),
            .emac_sop_final1   (emac_sop_final10),
            .emac_eop_final1   (emac_eop_final10),
            .emac_mod_final1   (emac_mod_final10),
            .mac_dest_port_en1 (mac_dest_port_out10[0]),
            .uni_in_busy1      (uni_cross_busy10),
            .mul_in_busy1      (mul_cross_busy10),
            .out_enable1       (out_enable10),
            .emac_len_final1   (emac_len_final10),
            //.emac_pri_final1   (emac_pri_final10),
            .read_finish1      (read_finish10),
            //with crossbar_ctl_top_2
            .emac_data_final2  (emac_data_final20),
            .emac_dval_final2  (emac_dval_final20),
            .emac_dsav_final2  (emac_dsav_final20),
            .emac_sop_final2   (emac_sop_final20),
            .emac_eop_final2   (emac_eop_final20),
            .emac_mod_final2   (emac_mod_final20),
            .mac_dest_port_en2 (mac_dest_port_out20[0]),
            .uni_in_busy2      (uni_cross_busy20),
            .mul_in_busy2      (mul_cross_busy20),
            .out_enable2       (out_enable20),
            .emac_len_final2   (emac_len_final20),
            //.emac_pri_final2   (emac_pri_final20),
            .read_finish2      (read_finish20),
            //with crossbar_ctl_top_3
            .emac_data_final3  (emac_data_final30),
            .emac_dval_final3  (emac_dval_final30),
            .emac_dsav_final3  (emac_dsav_final30),
            .emac_sop_final3   (emac_sop_final30),
            .emac_eop_final3   (emac_eop_final30),
            .emac_mod_final3   (emac_mod_final30),
            .mac_dest_port_en3 (mac_dest_port_out30[0]),
            .uni_in_busy3      (uni_cross_busy30),
            .mul_in_busy3      (mul_cross_busy30),
            .out_enable3       (out_enable30),
            .emac_len_final3   (emac_len_final30),
            //.emac_pri_final3   (emac_pri_final30),
            .read_finish3      (read_finish30), 
            //with MAC_0
            .emac_data_final   (pkt_data_o_0),
            .emac_dval_final   (pkt_dval_o_0),
            .emac_dsav_final   (pkt_dsav_o_0),
            .emac_sop_final    (pkt_sop_o_0),
            .emac_eop_final    (pkt_eop_o_0),
            .emac_mod_final    (pkt_mod_o_0),
            .emac_len_final    (/* tx_len_mac0 */)
            
        );
//第二列选择
    cross_clumn_select cross_clumn_select_1(
            //system in/out
            .clk               (clk),
            .rst_n             (rst_n),
            //with crossbar_ctl_top_0
            .emac_data_final0  (emac_data_final01),
            .emac_dval_final0  (emac_dval_final01),
            .emac_dsav_final0  (emac_dsav_final01),
            .emac_sop_final0   (emac_sop_final01),
            .emac_eop_final0   (emac_eop_final01),
            .emac_mod_final0   (emac_mod_final01),
            .mac_dest_port_en0 (mac_dest_port_out01[1]),
            .uni_in_busy0      (uni_cross_busy01),
            .mul_in_busy0      (mul_cross_busy01),
            .out_enable0       (out_enable01),
            .emac_len_final0   (emac_len_final01),
            //.emac_pri_final0   (emac_pri_final01),
            .read_finish0      (read_finish01),
            //with crossbar_ctl_top_1
            .emac_data_final1  (emac_data_final11),
            .emac_dval_final1  (emac_dval_final11),
            .emac_dsav_final1  (emac_dsav_final11),
            .emac_sop_final1   (emac_sop_final11),
            .emac_eop_final1   (emac_eop_final11),
            .emac_mod_final1   (emac_mod_final11),
            .mac_dest_port_en1 (mac_dest_port_out11[1]),
            .uni_in_busy1      (uni_cross_busy11),
            .mul_in_busy1      (mul_cross_busy11),
            .out_enable1       (out_enable11),
            .emac_len_final1   (emac_len_final11),
            //.emac_pri_final1   (emac_pri_final11),
            .read_finish1      (read_finish11),
            //with crossbar_ctl_top_2
            .emac_data_final2  (emac_data_final21),
            .emac_dval_final2  (emac_dval_final21),
            .emac_dsav_final2  (emac_dsav_final21),
            .emac_sop_final2   (emac_sop_final21),
            .emac_eop_final2   (emac_eop_final21),
            .emac_mod_final2   (emac_mod_final21),
            .mac_dest_port_en2 (mac_dest_port_out21[1]),
            .uni_in_busy2      (uni_cross_busy21),
            .mul_in_busy2      (mul_cross_busy21),
            .out_enable2       (out_enable21),
            .emac_len_final2   (emac_len_final21),
            //.emac_pri_final2   (emac_pri_final21),
            .read_finish2      (read_finish21),
            //with crossbar_ctl_top_3
            .emac_data_final3  (emac_data_final31),
            .emac_dval_final3  (emac_dval_final31),
            .emac_dsav_final3  (emac_dsav_final31),
            .emac_sop_final3   (emac_sop_final31),
            .emac_eop_final3   (emac_eop_final31),
            .emac_mod_final3   (emac_mod_final31),
            .mac_dest_port_en3 (mac_dest_port_out31[1]),
            .uni_in_busy3      (uni_cross_busy31),
            .mul_in_busy3      (mul_cross_busy31),
            .out_enable3       (out_enable31),
            .emac_len_final3   (emac_len_final31),
            //.emac_pri_final3   (emac_pri_final31),
            .read_finish3      (read_finish31), 
            //with MAC_1
            .emac_data_final   (pkt_data_o_1),
            .emac_dval_final   (pkt_dval_o_1),
            .emac_dsav_final   (pkt_dsav_o_1),
            .emac_sop_final    (pkt_sop_o_1),
            .emac_eop_final    (pkt_eop_o_1),
            .emac_mod_final    (pkt_mod_o_1),
            .emac_len_final    (/* tx_len_mac1 */)
             
        );
//第三列选择
    cross_clumn_select cross_clumn_select_2(
            //system in/out
            .clk               (clk),
            .rst_n             (rst_n),
            //with crossbar_ctl_top_0
            .emac_data_final0  (emac_data_final02),
            .emac_dval_final0  (emac_dval_final02),
            .emac_dsav_final0  (emac_dsav_final02),
            .emac_sop_final0   (emac_sop_final02),
            .emac_eop_final0   (emac_eop_final02),
            .emac_mod_final0   (emac_mod_final02),
            .mac_dest_port_en0 (mac_dest_port_out02[2]),
            .uni_in_busy0      (uni_cross_busy02),
            .mul_in_busy0      (mul_cross_busy02),
            .out_enable0       (out_enable02),
            .emac_len_final0   (emac_len_final02),
            //.emac_pri_final0   (emac_pri_final02),
            .read_finish0      (read_finish02),
            //with crossbar_ctl_top_1
            .emac_data_final1  (emac_data_final12),
            .emac_dval_final1  (emac_dval_final12),
            .emac_dsav_final1  (emac_dsav_final12),
            .emac_sop_final1   (emac_sop_final12),
            .emac_eop_final1   (emac_eop_final12),
            .emac_mod_final1   (emac_mod_final12),
            .mac_dest_port_en1 (mac_dest_port_out12[2]),
            .uni_in_busy1      (uni_cross_busy12),
            .mul_in_busy1      (mul_cross_busy12),
            .out_enable1       (out_enable12),
            .emac_len_final1   (emac_len_final12),
            //.emac_pri_final1   (emac_pri_final12),
            .read_finish1      (read_finish12),
            //with crossbar_ctl_top_2
            .emac_data_final2  (emac_data_final22),
            .emac_dval_final2  (emac_dval_final22),
            .emac_dsav_final2  (emac_dsav_final22),
            .emac_sop_final2   (emac_sop_final22),
            .emac_eop_final2   (emac_eop_final22),
            .emac_mod_final2   (emac_mod_final22),
            .mac_dest_port_en2 (mac_dest_port_out22[2]),
            .uni_in_busy2      (uni_cross_busy22),
            .mul_in_busy2      (mul_cross_busy22),
            .out_enable2       (out_enable22),
            .emac_len_final2   (emac_len_final22),
            //.emac_pri_final2   (emac_pri_final22),
            .read_finish2      (read_finish22),
            //with crossbar_ctl_top_3
            .emac_data_final3  (emac_data_final32),
            .emac_dval_final3  (emac_dval_final32),
            .emac_dsav_final3  (emac_dsav_final32),
            .emac_sop_final3   (emac_sop_final32),
            .emac_eop_final3   (emac_eop_final32),
            .emac_mod_final3   (emac_mod_final32),
            .mac_dest_port_en3 (mac_dest_port_out32[2]),
            .uni_in_busy3      (uni_cross_busy32),
            .mul_in_busy3      (mul_cross_busy32),
            .out_enable3       (out_enable32),
            .emac_len_final3   (emac_len_final32),
            //.emac_pri_final3   (emac_pri_final32),
            .read_finish3      (read_finish32),
            //with MAC_2
            .emac_data_final   (pkt_data_o_2),
            .emac_dval_final   (pkt_dval_o_2),
            .emac_dsav_final   (pkt_dsav_o_2),
            .emac_sop_final    (pkt_sop_o_2),
            .emac_eop_final    (pkt_eop_o_2),
            .emac_mod_final    (pkt_mod_o_2),
            .emac_len_final    (/* tx_len_mac2 */)
            
        );
// 第四列选择                
    cross_clumn_select cross_clumn_select_3(
            //system in/out
            .clk               (clk),
            .rst_n             (rst_n),
            //with crossbar_ctl_top_0
            .emac_data_final0  (emac_data_final03),
            .emac_dval_final0  (emac_dval_final03),
            .emac_dsav_final0  (emac_dsav_final03),
            .emac_sop_final0   (emac_sop_final03),
            .emac_eop_final0   (emac_eop_final03),
            .emac_mod_final0   (emac_mod_final03),
            .mac_dest_port_en0 (mac_dest_port_out03[3]),
            .uni_in_busy0      (uni_cross_busy03),
            .mul_in_busy0      (mul_cross_busy03),
            .out_enable0       (out_enable03),
            .emac_len_final0   (emac_len_final03),
            //.emac_pri_final0   (emac_pri_final03),
            .read_finish0      (read_finish03),
            //with crossbar_ctl_top_1
            .emac_data_final1  (emac_data_final13),
            .emac_dval_final1  (emac_dval_final13),
            .emac_dsav_final1  (emac_dsav_final13),
            .emac_sop_final1   (emac_sop_final13),
            .emac_eop_final1   (emac_eop_final13),
            .emac_mod_final1   (emac_mod_final13),
            .mac_dest_port_en1 (mac_dest_port_out13[3]),
            .uni_in_busy1      (uni_cross_busy13),
            .mul_in_busy1      (mul_cross_busy13),
            .out_enable1       (out_enable13),
            .emac_len_final1   (emac_len_final13),
            //.emac_pri_final1   (emac_pri_final13),
            .read_finish1      (read_finish13),
            //with crossbar_ctl_top_2
            .emac_data_final2  (emac_data_final23),
            .emac_dval_final2  (emac_dval_final23),
            .emac_dsav_final2  (emac_dsav_final23),
            .emac_sop_final2   (emac_sop_final23),
            .emac_eop_final2   (emac_eop_final23),
            .emac_mod_final2   (emac_mod_final23),
            .mac_dest_port_en2 (mac_dest_port_out23[3]),
            .uni_in_busy2      (uni_cross_busy23),
            .mul_in_busy2      (mul_cross_busy23),
            .out_enable2       (out_enable23),
            .emac_len_final2   (emac_len_final23),
            //.emac_pri_final2   (emac_pri_final23),
            .read_finish2      (read_finish23),
            //with crossbar_ctl_top_3
            .emac_data_final3  (emac_data_final33),
            .emac_dval_final3  (emac_dval_final33),
            .emac_dsav_final3  (emac_dsav_final33),
            .emac_sop_final3   (emac_sop_final33),
            .emac_eop_final3   (emac_eop_final33),
            .emac_mod_final3   (emac_mod_final33),
            .mac_dest_port_en3 (mac_dest_port_out33[3]),
            .uni_in_busy3      (uni_cross_busy33),
            .mul_in_busy3      (mul_cross_busy33),
            .out_enable3       (out_enable33),
            .emac_len_final3   (emac_len_final33),
            //.emac_pri_final3   (emac_pri_final33),
            .read_finish3      (read_finish33),
            //with MAC_3
            .emac_data_final   (pkt_data_o_3),
            .emac_dval_final   (pkt_dval_o_3),
            .emac_dsav_final   (pkt_dsav_o_3),
            .emac_sop_final    (pkt_sop_o_3),
            .emac_eop_final    (pkt_eop_o_3),
            .emac_mod_final    (pkt_mod_o_3),
            .emac_len_final    (/* tx_len_mac3 */)
            
        );

endmodule
